This invention relates to a memory refreshing control apparatus and a memory refreshing control method and, more particularly, to a memory refreshing control apparatus and a memory refreshing control method for controlling a memory which comprises a plurality of memory banks each necessitating a refreshing operation.
As is well known in the art, there are various types of memories one of which is a dynamic random access memory such as a DRAM, a synchronous DRAM (SDRAM), and so on. In a case where the dynamic random access memory is used as a data memory, it is necessary to carry out a refreshing operation (a refreshing request) in order to hold data in the memory. An apparatus for controlling such as a refreshing operation (a refreshing request) is a memory refreshing control apparatus.
On controlling the memory necessitating the refreshing operation by the memory refreshing control apparatus, contention for the memory may occur between a normal memory access request for reading and writing the memory and the refreshing operation (the refreshing request). Under the circumstances, a conventional memory refreshing control apparatus always makes either the memory access request or the refreshing request place in a wait state.
On the other hand, the memory where a memory space is divided into a plurality of memory subspaces is known in the art. Each memory subspace is called a bank memory. In addition, the bank memory may be called a memory bank or may be merely called a bank. Various memory refreshing control apparatuses for controlling the memory comprising a plurality of bank memories are known in the art.
By way of example, Japanese Unexamined Utility Model Publication of Jikkai No. H03-124,399 or JP-U H03-124339 discloses a memory control circuit which is capable of avoiding contention between a refreshing and a main memory access and of preventing performance degradation of a computer system. The memory control circuit according to JP-U H03-124339 comprises DRAM control means for controlling banks of a DRAM in one-to-one correspondence and the DRAM control means includes refreshing request means. In addition, the memory control circuit comprises a selector for decoding the memory access from an external to notify the respective banks of select/deselect. A refreshing request occurs when the memory access from the external is decoded and deselect of a bank is notified. In JP-U H03-124339, although the refreshing request and the normal memory access compete in the memory comprising a plurality of banks, the refreshing request and the normal memory access are concurrently processed if the refreshing request and the normal access are made for different banks.
In addition, Japanese Unexamined Patent Publication of Tokkai No. H06-68,671 or JP-A H06-68671 discloses a high-speed memory device without lowering a memory access time due to a wait for a refreshing operation by providing a refreshing controller and a refreshing timer. The memory device disclosed in JP-A H06-68671 comprises a plurality of memory banks having successive memory addresses, a memory controller, the refreshing controller, and refreshing timers for the respective memory banks. Each refreshing timer produces a maximum refreshing period. The memory controller supplies each memory bank with a reading control signal. The refreshing controller refreshes all of the memory banks except for one related to an access request at an earlier one of an access request occurrence time internal from an optional memory bank to the next memory bank and the maximum refreshing period. That is, the memory device disclosed in JP-A H06-68671 continuously monitors a normally accessed bank in the memory banks and simultaneously refreshes the memory bank except for the accessed bank although a normal access is performed at a refreshing timing.
Specifically, when a CPU fetches instruction from a first memory bank, a memory access request is outputted to the memory controller. The memory controller decodes the memory access request and outputs control signal group for reading memory only to the first memory bank. The first memory bank reads data according to the signal group and a memory address. In general, a period for reading program of the CPU is shorter than the refreshing period. When the demand for reading instruction is issued from a second memory bank after reading from the first memory bank, the refreshing of the first, a third, and a fourth memory banks is executed by means of the refreshing controller. Consequently, by successively refreshing all memory banks except for the bank for demanding memory access, the refreshing period is satisfied with the exception of a particular case.
Furthermore, Japanese Unexamined Patent Publication of Tokkai No. H07-141,862 or JP-A H07-141862 discloses a refreshing timing controller which is capable of suppressing contention between refreshing and access for an object to be refreshed by controlling refreshing timing as required. According to JP-A H07-141862, refreshing periods of each bank are measured by counters corresponding to a measuring section. When an access instruction from a CPU of a computer is issued, it is confirmed by a refreshing memory of a control section whether the banks performing access being refreshed or not. And when being refreshed, access is made a standby state until refreshing is finished. When not being refreshed, access is performed, while the banks out of an object of a refreshing period are refreshed first preceding a regular refreshing through the measuring section, effectively refreshed, also, contention between refreshing and access is suppressed for the banks being an object.
In addition, Japanese Unexamined Patent Publication of Tokkai No. H10-134,569 or JP-A H10-134569 discloses a synchronous-type dynamic random access memory which is capable of allowing a memory to effect a refreshing operation selectively and reducing the current consumption by a method wherein a memory cell array divided into multibanks and a circuit selecting the bank to be an object of entry/exit are provided. According to JP-A H10-134569, a self-refreshing bank selection circuit generates a bank selection signal in a self-refreshing mode. In the period of the self-refreshing mode, I/O buffers other than a clock input buffer to which a control signal is inputted are also in enable states to enable to command input continuously. In other words, although the power consumption can not be suppressed in comparison with a conventional synchronous type DRAM, as the refreshing operation is performed by a distributed refreshing method, the total current consumption can be reduced as a cycle time basis.
At any rate, each of JP-A H06-68671, JP-A H07-141862, and JP-A H10-134569 discloses a memory device comprising refreshing timers (refreshing counters) for respective banks.
However, the above-mentioned JP-U H03-124339, JP-A H06-68671, JP-A H07-141862, and JP-A H10-134569 are disadvantageous in that the number of parts (amount of hardware) is increased because of providing with refreshing request arrangements or refreshing timers (refreshing counters) for respective bank memories (memory banks).
In addition, JP-A H10-134569 may disclose a conventional synchronous-type dynamic random access memory comprising only one refreshing counter for all device as a counter for generating a low address signal for self-refreshing. However, the refreshing counter is for making all of the banks execute refreshing operation at once and it is impossible to make an individual bank execute the refreshing operation.